A low-complexity fully scalable interleaver/address generator based on a novel property of QPP interleavers

5-th generation mobile networks aim the peak data rates in excess of few Gbs, which may appear to be challenging to achieve due to the existence of some blocks such as the turbo decoder. In fact, the interleaver is known to be a major challenging part of the turbo decoder due to its need to the parallel interleaved memory access. LTE uses Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for the parallel decoding. In this paper, a new property of the QPP interleaver, called the correlated shifting property, is theoretically proved, leading to a fully scalable interleaver and a low-complexity address generator for an arbitrary order of parallelism. The proposed interleaver reduces the required addresses in half. Moreover, the scalability of the proposed interleaver proves up to 51% lower power consumption compared to the best reported interleaver to-date.